The present invention relates to a digital parallel computing circuit for positive and negative binary numbers, the latter having to be represented in two's complement for forming the product of a first binary number and a second binary number and then adding a third binary number by means of an adder consisting of full-adder stages and by means of a multiplier consisting of full adders arranged in columns and rows and each having an AND gate associated therewith, which AND gates may be omitted in the output row.
Multipliers of such design are described in detail, for example, in a book by A. Shah et al,"Integrierte Schaltungen in digitalen Systemen", Vol. 2, Basel, 1977, pp. 171 to 193 and 211 to 216, see particularly FIGS. IX.62 to IX.66, IX.67, and IX.77 on pages 172, 174 to 177, and 212. All these multipliers are parallel multipliers, in contrast to the serial and parallel-serial multipliers dealt with elsewhere in that book. For high-speed multiplications as are required in digital signal processors, only the aforementioned parallel multipliers are suitable, and the multipliers used in the present invention are only parallel multipliers.
As follows from the Proceedings of the "9. Internationaler Kongress Mikroelektronik", Munich, Nov. 10-12, 1980, pages 56 to 62 and 105 to 108, the basic arithmethic operation in such high-speed signal processors consists in the formation of the product of two binary numbers and the subsequent addition of a third binary number. The signal processor shown on page 62 of those Proceedings includes a high-speed multiplier followed by an adder. The arithmetic unit shown on page 108 is only described as consisting of a multiplier and an adder.
The adders of the prior art just mentioned are, of course, parallel adders, whose computation time is determined essentially by the time required to form the carry of the most significant digit, cf. the above-mentioned book by A. Shah et al, pages 92 to 117. If an arrangement as disclosed in the second-mentioned reference is chosen, i.e., a multiplier followed by an adder, the computation time of the adder adds to that of the multiplier. On the other hand, however, the computation time of the multiplier is determined essentially by the computation time of the full adders in the output row of the multiplier, because the carry up to the most significant digit of the product must be generated in this row. In some designs of such multipliers, this output row is a complete parallel adder, see FIGS. IX.63 to IX.65 of the first-mentioned book by A. Shah et al. The computation time of the parallel computing circuit consisting of a multiplier followed by an adder is thus composed of that of the multiplier without output row, that of the output row, and that of the adder, the two latter computation times being approximately equal, while the former is smaller than the two latter by a factor of about 2 to 4.